Relais based Audio Attenuator

First, many thanks to Jos van Eijndhoven
[http://www.eijndhoven.net/jos/index.html]
[http://www.eijndhoven.net/jos/relaixed2/index.html]
He has done a great work on evaluate the math basics to create log (dB) scaled resistor dividers with a minimum amount of switches.
Also, he wrote a programm to easy calculate the required reistance values.
It's a good starting point and even for the advanced user, his circuits are more than ever necessary.

But his circuit design has some drawbacks, that will be analyzed here into deep:


Introduction

The standard way for electronic volume control are CMOS switches, almost integrated into ICs since many years. But this devices have some drawbacks:
- increased harmonics by silicon resistors
- increased harmonics by silicon switches and their drawbacks, mostly unwanted capacity and  ON-resistance
- increased noise wich is topology dependent and can't be decreased further than possible today (~ 4µV .. 16µV at the output)

All the integrated devices are expensive and even the top products have the problems mentioned above. Don't to be missunderstood,
they do a great job, but in the end, it's possible to do it better.....

With the work of   Jos van Eijndhoven, mentioned above, it's possible to use a usable amount of relais to switch in logarithmic steps.
The noise and the distortion then only depends on the used OpAmps, the choosen resistors, the layout and the used relais.

Relay choice

Most people starts with conventional relais at this point, overlooking that there are minimum currents and voltages given in the datasheet, if given.
The reason for this minimum ratings is the contact itself, wich will not close perfectly and more imperfect as lower the current and voltages are.

There exist some signal-relais types and only they have given this minimum ratings wich are fairly high for this usecase, typ. in the 1..10mV and 10..100µA range.
Now, think of the last contact in the log. scaled chain.. it will switch ~ -60dB below fullscale a resistance of several 100k ohms.
If you have 1Vrms in, this contact will see only 1mV and a handfull of µA.That's hard on the edge that it will close perfectly and only if it is "new".
After several years of use, it will degrade and the relais must be replaced because of bad contacts

There's an other type of relay, often overlooked, but very usefull here. It's called REED-relay. For the internal construction, please have a look on the datasheet and Appnotes.
[Meder, Appnote  ]
In the end, it's contacts are designed for µV and pA of voltage and current. That's what we need here !
The drawback is, that they are a little more expensive than the "standard" type, roughly the price is quad the price for a standard relay.
Also, dual contacts and especially SPDT types are rare and only SPST types are widely available.

Because of that, the SPDT type in the log chain must be exchanged by two SPST relais.
But this opens the opportunity to do either "make-before-break", "break-before-make"  or  "simultanous" switching.

One, very small, drawback should not be concealed here:
The REED contacts will create a thermo voltage of several µV if both ends have different temperature levels.
[* Meder, Appnote ]
So it is advisable to use only the minimum necessary voltage to switch them, but see next chapter....

Relay control

As mentioned above, with SPST types only, you can control the switch behaviour for every single relais and this possibility should be used.
So, for a 7 step attenuator, you will need 14 SPST relais wich will give 14 relais to be controlled.

I/O Interface

In most cases, you controller will not have enough GPIOs to control all the necessary relais and switches.
Therefore, you will need something like an "Port-Expander". There exist at least 3 types:

I2C-Expander

They will be controlled (like it's name) by I2C. They exist mostly in 8-Bit and 16-Bit variants, sometimes with configurable adresses.
There are some manufacturers with sometimes identical devices, like TI, NXP, Microchip. This devices are not cheap.

SPI-Expander

They will be controlled (like it's name) by SPI. They exist mostly in 8-Bit and 16-Bit variants.
There are some manufacturers with sometimes identical devices, like TI, NXP, Microchip. This devices are not cheap and not that wide spread as the I2C ones.

Shift Register 

They will be controlled by a SPI-style interface with some additional pins. The most known type is the 595 type in various variants (HC,HCT,LVC,....).
They are widely spreaded and cheap. Before buying a specialized IC, think of use shift registers, but use series resistors to damp the sharp edges on the tracks.


Relais Driver

As mentinoed above, only the min. necessary voltage for the relais to "hold" should be used, but the initial voltage until the relay has switched over must be higher,
e.g  if you have a 12V relais, you should use 10V .. 12V to turn it on and then switch back to 5V..8V to hold it.

One possibility is to use a capacitor wich is connected across a Z-diode to give a "turn-on" kick, but this will lead to very high capacitances if the relais-coil has verly low resistance.
To advance this circuit, one (or two) transistors can be added to short-circuit the Z-diode for some ms:

PIC

Here, an additional Transil or Z-Diode (Z2) is used in series with the standard freewheel diode. This additional diode allows the coil to develop more flyback voltage but also decrease OFF time dramaticly. Hint: Vccrelais + Vz must be lower than the breakdown voltage of the transistor !
[* ]

This will work, but unfortunately, this circuit is necessary for every relais used, so in our case we will need it 14 times per channel.....

Analog regulator

To keep it simple, the Relais + Voltage can be make variable with slightly increasing and decreasing levels,  this can also be done by  a PWM controlled by a processor, see picture:



Please observe the slightly higer Vcc, wich is necessary to overcome the voltage loss in T4/T5 (~1,2V)  and the limited headrom of OP1 (~1 V).
The OPs gain must be set by R5 and R6 in that way, that for 100% dutycycle, the output voltage will reach OPs Vcc, C2 is for compensating the slow T4/T5 combination.
T4 must be capable of dissapate the Voltage Drop multiplied by the current. In our example (7-step attenuator, 2 Channel) at maximum 7*2 relais can be active.
With a relay current of ~ 50mA, this will create 0,7A current. If a voltage drop of 5V is applied, this will lead to 3,5 W dissapated power.... not that funny....

Switch mode regulator

If possible for layout, a controlled switchmode regulator could be used:

PWM controlled Buck converter (BUCK has reference relative to Vout)

If R5 = R6, then the output voltage is always 2*Vref higher than the OP output.
R5 = R6 -> Vout = ((1+R7/R8) * PWMdc) + 2 * Vref Buck.
Please observe, that the voltage at the OP output should only be changed slowly (< 50 Hz), else the Buck could get out of regulation !




PWM controlled Buck converter (BUCK ref. relative to GND), schematic
Use PWM frequency of 100 kHz or more


PWM controlled Buck converter (BUCK ref. relative to GND), transfer function

For the control PWM frequency, choose a range that will be well low-pass filtered by R3/C1, wich will result in fpwm >> 100 Hz for 47k/1µF.
To not have the PWM routed by long traces (radiation !), it would be wise to  put the R3/C1 combination directly beside the generting controller pin.

If using one ot the methods above, the Vccrelais can be rised before switching events and lowered after that.

Using the Relais switching transistor (e.g. T1 or T2 here) with PWM to reduce current comnsumption
will result in having the PWM pulses on the relais coil wich could be transferred into the signal path by the magnetic field !

Clickless switching

DC removal

The main step to avoid "clicks" while changing Volume is to avoid DC.
One possibility is to AC-couple with electrolytics, but they are not the best choice regarding signal quality.....
The other possibility is one (or more) DC-Servos wich acts as a Highpass with 0.1 Hz (or below) corner frequency.

To be "click" free, the most important point to place a DC-servo is the input OP, directly before the stepped resistors.
Here, every µV counts for clickless operation, so that the right DC-servo OP should be choosen.

But also DC-servo OPs  have drawbacks:

1) input bias and input offset current
Because of DC-Servos have normally a very high input impedance (1 Meg), so that this impedance multiplied by the input bias currents will give additional DC,
wich will let to several mV offset in worst case, e.g. 500nA bias current (typical OP) multiplied by 1 MOhm (also typical for a servo) would add  500mV  DC-offset !

Select an OP with very low bias currents, best < 500pA

2) input noise voltage
This input noise is transferred directly to the output, without to be affected by the servo-loop !   

Select an OP with very "low" noise voltage spec, best < 8nV/sqrt(Hz)

3) input offset voltage
The OPs internal offset voltage will be directly transferred to the output and not regulated by the servo-loop !

Select an OP with very "low" offset voltage spec, best < 500µV
In worst case, if 1) and 2)  are given, use a single OP and trim the Offset with resistors (instead of a trimpot).


There's the minor problem of the bias currents of the OPs directly after the stepped attenuator.
If calculating the resistances and the topology, please choose a constant ouput resistance and make it in the 200 to 600 Ohms range.
This will give a small and predictable, constant DC voltage at the output, because the DC at the ouput will be
the (almost) constant output resistance of the ladder multiplied by the (almost) constant bias current and normally below 1mV. If really necessary,
a DC-servo could also be added in this stage.

Some advised OP types
Type Positive Negative
TL071 FET-input type, very low bias, cheap several mV offset wich must be trimmed, "high" noise
TL072/74 FET-input type, very low bias, cheap several mV offset wich cannot be trimmed directly, "high" noise
OPA134  FET-input type, very low bias   several mV offset wich must be trimmed directly, "high" noise, expensive
OPA134  FET-input type, very low bias   several mV offset wich cannot be trimmed directly, "high" noise, expensive
OPA604 FET-input type, very low bias   several mV offset wich must be trimmed directly, "high" noise, expensive
OPA2604 FET-input type, very low bias   several mV offset wich cannot be trimmed directly, "high" noise, expensive
OPA197/2197 Very low bias, Low noise, low offset expensive
TLV07 Very low bias, Low noise, low offset Attention on Vcc and differential input voltage !


ZeroCross switching

The second step to avoid "clicks" is the right timing by only switching when the voltage is "0" (in best case) or very small (practible).
If using REED relais, as suggested above, than you are happy with a really fast switching device.
They have switching times around 0.5 ms for ON and 0,1 ms for OFF if using the "72" type ones.

Now, you can add a signal window comparator with several 100 mV around  "0" and generate an interrupt for the µC if the signal is entering the window.
Be carefull if using PortExpander (SPI or I2C) because you will need time to get the data in.



Analog path


Remark: This is only a sheme, not a complete functional circuit !

Input stage

The input stage consist of the instrumental amplifier build with OP1 and OP2. The DC-Servo is realized with OP3 (see above).
In this configuration, the minimal achievable gain is 2.0, higher gains are possible.

If  using NE5532 or comparable OPs (~6 nV/sqrt(Hz)), the input stage will create ~ 3,1 µV noise (1 Hz - 22 kHz)  (R1 - R4 = 1k5; R5=1M ; R7=R8=100R)
This sounds much, but to be honest, the input stage has a gain of 2, so 1 Vrms IN will be 2Vrms OUT.
This will give noise figures of  ~ -116 dB / 2 Vrms or ~ - 125 dB / 6 Vrms.
The good news are, that with every reduction in the following ladder, the noise of the input stage will also be reduced. Using 6 dB reduction in level will  give -6 dB of noise.

Please see the input stage discussion in a later chapter. Link: Input Stages and Noise

Ladder network

If you design for 600R output impedance, 1 dB steps and have 7 steps, the noise will be always below 1µV for the ladder only.
So, the ladder noise will contribute less than the OPamps can do ever.

Output stage

The output stage is realized with OP4 wich is also the buffer for the ladder network.
The OP5 and R14,R15, forms a non-inverting DC-Servo and cancels out the DC. It can be removed, if not necessary.
Please keep in mind, that the output stage must have a gain > 1 (noninverting amplifier).
Gainout = 1 + R12/R13,  with  R12 = 1k5 (to not overload OP4 and OP5), and  10k for R13, the Gainout is ~ 1,15.

If  using NE5532 or comparable OPs (~6 nV/sqrt(Hz)), the output stage will create ~ 1,3 µV noise (1 Hz - 22 kHz)  (R12=1k5; R13=10k)
This will give noise figures of  ~ -118 dB / 1 Vrms or ~ -128 dB / 3 Vrms.
Using R12=1k5 ; R13=47 k will decrease noise further down to 1,2 µV, but in the end has no real impact on the noise figures.

Please see the output stage discussion in a later chapter. Link: Output Stage and Noise

Resistor choice

Resistors have different THD figures dependent of the material and the type (thick-film, thin-film, wound, pressed coal, ....)

Metall type Thin- and thick film reistors in SMD packages are widely available and should be the choice.

Avoid coal type reistors.

Wire wound ones are very good regarding THD, but the drawback is the high capacitance and the inductivity inside them. They should be avoided here.

As smaller resistors are, as less power they can dissapate. As more temperature change you have, as more the resistance vary.
With this two simple sentences, you can explain why transistors will create THD.
Imagine a sinewave wich will reach the max. Power for the resistor in the peak of the sinewave.
Then, and especially at low frequencies,  the resistor will heat up with signal amplitude and therefore the resistance will vary with signal amplitude wich will create distortion.
This is also the explanation of the not that good THD of the integrated volume controls, their internal resistances are that small, that internal heating with the signal cannot be avoided.
(Beside the fact that they are not of  metall-film type but edged in silicon)

So, keep in mind, that you, in general, should use as large resistors as possible, at minimum 1206 SMD types.
They can handle up to 125mW, so using them with ~ <20mW max/peak Power should give very low THD figures.
If more than one resistor is in a chain, the current flowing thru them will be set by the resistance sum and the power dissapation by the square of the current multiplied by the resistance value.
If using low value resistors (< 100 Ohms) and the current thru them is small ( < 5mA ), also 0805 types can be used.
Also solder them on big SMD-pads with huge traces will help to avoid signal dependent self heating because of the high thermal mass.

Resistors in 1206 package have a thermal resistance of ~200 K/W and 250 K/W for 0805 packages. (resistance to air !, not thermal mass )
20 mW * 200 K/W = 4K temperature rise ; 20 mW * 250 K/W = 6K temperature rise.



Avoid 0603 and smaller resistors if lowest THD is a concern.

e.g. 3Vrms = 4,5Vpk; total Resistance = 900 Ohms --> Current = 5mApk
Using one single 900R resistor will give 22.5 mW of PeakPower
Using two 420R resistors and one 60R resistor in series will give 10.5mWpk in each 420R resistor and 1.5mW in the 60R resistor.
The choice should be using 2 x 420R/1206 and 1 x 60R/0805 in series.

e.g. 3Vrms = 4,5Vpk; total Resistance = 1500 Ohms --> Current = 3mApk
Using one single 1k5 resistor will give 13.5 mW of PeakPower wich will be the upper end of what a 1206 resistor should dissapate without increased THD.

Also on the higher resistance value end, there are effects making reistors more bad than at the other end. Avoid using single 1 Meg or higher value resistors.
Build them up as a series combination of 470k max. resistors.

Moto controlled Pot

How to connect

If you update an existing device, it can be funny to reuse the old Pot, especially if using a motor driven one.
But if it is of the log type, it's not easy to get the current position. The trick is now to add a pararallel resistor from whiper to Vref to (almost) convert log to lin.
It will never work ideal, but if using an ADC, it helps....

The only drawback is, that you must now get the ADC voltage at some sample points and then interpolate the Potentiometer position.
Best practice is to divide the full ADC range into 8 or 16 subsections and interpolate inside this subsections.
If your pot has 270° rotation previously and you would now set 1dB steps within a 127 dB range, you have roughly 2° per step.
Especially on the "low" end, this could be critical.







In the picture "Connection for ADC use", the parallel HI resistor has a value of  0,03 * Rpottotal, so using a 100kpot,
Rhipar = 3k would be good choice. Care must be taken to not overload the lower resistance part. If using pots with 10k or less,
the current thru the lower resistor will be ~ 10 mA if the rotation is near to the end !



For Pot resistance values of 10k and lower, a Rpar of 0,1 would be the better choice (3V3 / 1k = 3,3mA).

Please keep in mind, that the given values in the pictures are only rough estimations for the attenuation.
It highly depends on the manufactur of your pot, how the resistance change with rotation !

Algorithm for auto Adjustment

Method 1

1)    Create a minimal pulse possible, so that the pot value changes.
2)    Measure the voltage with the ADC and enter it with the pulse count into a table
3)    Forward at 1) until there are no more changes in the ADC value (beside some noise).

Now you should have a table with many positions and the corresponding ADC value.
In best case, you have more than 1024 positions and you can interpolate between them.

Method 2

1)    Drive the pot to one of the ends.
2)    Drive the pot to the other end and measure the time to do that.
3)    Divide this time into 256 steps
4)    Drive again from one end to the other and  every 1/256 time step, you can measure the ADC value.


Motor driver

It would be wise to be able to adjust the pot speed from controller, at least in two steps, fast and slow.
Please see the chapter Switch mode regulator how to do this.

In the end, you don't develop a motor driver out of dicrete transistors anymore. There exist total integrated H-bridges,
in best case with over temperature and over current shutdown. The most known solutions seems to be:

L293 ST DIL, good and available 2,00 €
L298 ST SMD + TO220-11 2,40 € / 6,30 €
L6202 ST DIL 3,85 €
ZXMHC6A07T8TA Zetex SMD H Bridge FETs 1,15 €
DRVxxx TI cheap at Mouser, not available at smaller stores
LB 1641 Sanyo cheap, SIL (THT), no further info 1,25 €
A3967 Allegro SMD 2,99 €

(All pricing from Germany, mid 2017)

Voltage for Slow rotation




Layout and track routing

Please consider that GND is not GND !
Using a GND plane with every signal connected there is good for digital stuff, but it's worst for Audio (or analog in general).

Therefore, use a Signal-GND (SGND) with only once (wich means only once) connected to your system GND.  
Best practice is to pick it near the output of your device and rely every signal to this track.
You need an additional GND-Plane (e.g. for bypassing opamps), but you should never connect your SGND here,
except exactly once at one point. Use a spereate SGND for every channel.
The only thing wich must be observed is, that no current except the audio signal can flow through this track. Make it as wide as possible (0.4mm).
Take care, that no supply currents (e.g. from th bypass caps) can flow directly or nearby your SGND <-> GND connection. You can choose the PowerSupply connector directly as your connection point, but be aware that the supply current is also flowing thru this node !

If you use digital stuff (e.g. controller) and the relais driver, use a seperate DGND and never connect it to your SGND or GND.
Connect the OPamps bypass caps to the GND plane, not to the SGND track. The SGND must be treated as a signal, not a potential or plane !
To get maximum CommonModeRejection (unwanted signals) use 0.1% ( or better) resistors for R1 .. R4.






That advises are also valid for differential signal chains.


Input Stages and Noise

Classic 3 OPamp Input Stage



This (classic) approach gives high input impedance and good CMMR, if the resistors R1...R4 are 0.1% tolerance.
If R2=R4 and R3=R1, then the gain is set by gain = R2/R1.

R5 is connected to AGND to allow some CommonMode but not let it be too high.

One OPamp simple input stage



This (classic) approach gives only medium input impedance and only good CMMR, if the resistors R1...R4 are 0.1% tolerance and the output impedance of the previous stage is equal in both wires.
If R2=R4 and R3=R1, then the gain is set by gain = R2/R1.

It's simplicity has the drawback of high noise, poor CMRR in worst case and endless input impedance. Reducing the resistors will decrease input impedance and load the previous stage.

R5 is left away for clarity.

Two OPamp input stage (standard)


This (classic) approach gives high input impedance and good CMMR, if the resistors R1...R4 are 0.1% tolerance.
If R1=R2=R3=R4, then the gain is 2.0. This stage can never produce a gain lower than 1.

It should be observed, that the first OP always have a gain > 1 (in the example gain is 2), so that IN- * gain could overdrive the first OP output.
If used in single ended configuration, this will never occur because the IN(-) (hopefully) never sees more than some mV.

Second, if used in the configuration with gain = 2.0, the output is hard driven into high level, if the input voltage is higher than 2 Vrms.
(e.g. input = 3Vrms --> 4.2Vpk * 2.0 = 8.4Vpk at output)

R5 is left away for clarity.

Two OPamp input stage (low gain)



This (classic) approach gives high input impedance and good CMMR, if the resistors R1...R4 are 0.1% tolerance.
Here the the gain is reduced to 1.1 to avoid output overdrive (see text before)

It should be observed, that the first OP always have a gain of  10, so that IN- * gain could overdrive the first OP output.
If used in single ended configuration, this will never occur because the IN(-) (hopefully) never sees more than some mV.

R5 is left away for clarity.

Two OPamp input stage (low gain, switchable)



This (classic) approach gives high input impedance and good CMMR, if the resistors R1...R4 are 0.1% tolerance.
Here the the gain can be selected as 1.1 or 2.0.

This circuit is almost the same as the previous one, but with a low gain for high input voltages and a switchable gain for lower input voltages.

It should be observed, that the first OP always have a gain of  10, so that IN- * gain could overdrive the first OP output.
If used in single ended configuration, this will never occur because the IN(-) (hopefully) never sees more than some mV.

R5 is left away for clarity.

Two OPamp input stage (low gain, low noise)




This (classic) approach gives high input impedance and good CMMR, if the resistors R1...R4 are 0.1% tolerance.
Here the the gain is reduced to 1.1 to avoid output overdrive (see text before)
Further, the resistance values of the first OPamp are reduced to reduce output noise.
R1 could also be doubled to 300R and R2 = 3k, wich will reduce CMMR error introduced by solder joints (0.1% of 150R are 0.15R, not that much !)

It should be observed, that the first OP always have a gain of  10, so that IN- * gain could overdrive the first OP output.
If used in single ended configuration, this will never occur because the IN(-) (hopefully) never sees more than some mV.

R5 is left away for clarity.

Two OPamp input stage (low gain, low noise, variable gain)

This (classic) approach gives high input impedance and good CMMR, if the resistors R1...R4 are 0.1% tolerance.
Here the the gain is reduced to 1.1 to avoid output overdrive (see text before) if SW is open.
Further, the resistance values of the first OPamp are reduced to reduce output noise.
R1 could also be doubled to 300R and R2 = 3k, wich will reduce CMMR error introduced by solder joints (0.1% of 150R are 0.15R, not that much !)

The gain can be increased by closing SW, 185,4 Ohms give a factor of 2.0
The gain can be calculated as Gain = 1 + (R1/R2) + ((R1+R2)/Rgain), if R1/R2 = R4/R3


It should be observed, that the first OP always have a gain of  10, so that IN- * gain could overdrive the first OP output.
If used in single ended configuration, this will never occur because the IN(-) (hopefully) never sees more than some mV.

R5 is left away for clarity.

Input stage variants noise figures


Circuit Output noise
[µVrms]		 Output noise
[dBu]		 Output noise
[dB]
rel. 1Vrms @ input		 Pro/CON
One OPamp simple input stage, gain = 1.0 4,2 - 105,3 - 107,5 - high noise
+ 1 OPamp
+ gain < 1 possible
Three OPamp Input Stage, gain = 1.0 2,4 - 110,2 - 112,4 - high noise
- 3 OPamps
+ gain < 1 possible
Two OPamp input stage (standard), gain = 2.0 2,7 - 109,2 - 117,4 - high output voltage
+ good noise
* Two OPamp input stage (low gain), gain = 1.1 1,6 - 113,7 - 116,8 + good noise
* Two OPamp input stage (low gain, switchable), gain = 2.0 2,7 - 109,2 - 117,4 + good noise
Two OPamp input stage (low gain, low noise), gain = 1.1 1,5 - 114,3 - 117,3 - low resistor values
+ best noise
Two OPamp input stage (low gain, low noise), gain = 2.0 2,5 - 109,8 - 118,1 - high output voltage
- low resistor values
+ best noise

All noise figures were calculated with NE5532 equivalent input noise figures.
* Preffered configurations

Output Stage and Noise



This approach seems to be classical, but includes some small enhancements.
First, R7/R18/C1 and  U2 form the DC Servo circuit. It's output is inverted by OP2 and R5/R6.
To limit the noise generated by the servo and the inverter, its added into OP1's feedback path
with a gain << 1 (g=R1/R2, inverting amplifier, here: 1k5/7k5= 1/5).

The signal gain is 1 + R1/R2, becoming ~ 1.2 here.

C2 and C3 are for stability reasons only and not necessary under normal working conditions.

If the output gain should be switchable (e.g. by relais), OP1's feedback network is extended by a resistor to SGND (R3).
The signal gain is then 1 + R1/(R3//R2), becoming ~ 2.4 here.

Drawback: The gain should not be switched without muted outputs, because the DC-Servo will multiply the DC at the input by the gain difference
while switching, so plopps will occur.
If the DC at the input is small enough, it's not harmfull but avoiding it is better :-)
e.g.:
Routladder = 600R * Ibias OP1 = 1µA + OP1 DC Offset = 3mV will result in 4 mV DC at the input
4 mV DC * 2 = 8mV "plopp" at the output, wich is very small but not unhearable.

Gain Output noise
[µVrms]		 Output noise
[dBu]		 Output noise [dB]
rel. 1Vrms
@ OutStage input		 Output noise [dB]
rel. 100mVrms
@ OutStage input
gain = 1.2 (+1,6 dB) 1,32 - 115 - 119,3 - 99,3
gain = 2.0 (+6,0 dB) 1,94 - 112 - 120,2 - 100,2
gain = 2.4 (+7,6 dB) 3,04 - 108 - 117,9 - 97,9